Welcome!
You have arrived at the entry point for access to the online resume
of C. McCord.
Revision F., last modified 01/14/97
The following pages are in the process of being redesigned for both viewing on the WWW and
for printing from the Netscape "file, print" command. As a result, some
data not appropriate for inclusion in a printed resume has been included
on this introductory page. If you select resume1996, you may notice some
redundancy. If you select resume1997, you will find it under
construction.
Currently fully employed but always ready to consider a project with a
very high degree of difficulty!
LONG TERM GOAL: Relocation to Colorado, Utah, Wyoming, or Montana.
HOTTEST activities:
Evaluation of Verilog, VHDL, and schematic capture as they pertain to
the design of high speed logic implemented in Actel and Xilinx FPGAs.
schematic capture vhdl verilog design pcad allegro consultant aix unix
system,engineer,system,engineer,system,engineer,system,engineer,system,engineer,system engineer,
simulation,engineer,simulation,engineer,simulation,engineer,simulation,engineer,simulation,engineer,
Evaluation of VHDL designs failing to meet speed and size requirements
and subsequent conversion of such designs to
a hierarchical schematic format more suitable for compact high speed
designs.
schematic capture vhdl verilog design pcad allegro consultant aix unix
actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,
fpga,field,programmable,gate,array,fpga,field,programmable,gate,array,fpga,field,programmable,gate,array,
Design of high bandwidth DRAM based data storage systems.
schematic capture vhdl verilog design pcad allegro consultant aix unix
actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,actel,xilinx,
PLEASE e-mail me if you are confused or have any difficulty
deciphering this site.
If you found this page with a search engine, I would appreciate a short
e-mail listing the one you used; thanks.
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NOTE: Most of the job descriptions are actually links to other
documents providing much more information about that job.
shematic capture vhdl verilog design pcad allegro consultant aix unix
fpga actel xilinx engineer system simulation realtime
fpga actel xilinx engineer system simulation realtime
shematic capture vhdl verilog design pcad allegro consultant aix unix
shematic capture vhdl verilog design pcad allegro consultant aix unix
fpga design fpga design fpga design fpga design fpga design fpga design
verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl
fpga design fpga design fpga design fpga design fpga design fpga design
verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl
fpga design fpga design fpga design fpga design fpga design fpga design
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
fpga actel xilinx engineer system simulation realtime
fpga actel xilinx engineer system simulation realtime
shematic capture vhdl verilog design pcad allegro consultant aix unix
shematic capture vhdl verilog design pcad allegro consultant aix unix
fpga design fpga design fpga design fpga design fpga design fpga design
verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl
fpga design fpga design fpga design fpga design fpga design fpga design
verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl verilog vhdl
fpga design fpga design fpga design fpga design fpga design fpga design
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx
shematic capture vhdl verilog design pcad allegro consultant aix unix
actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx actel xilinx