Contract Employment
Jan. 1996 to present
IBM Corp., Dept. 2S9, Server Performance Analysis,
Research Triangle Park, NC.
Design Engineer, duties include:
Subsystem, module, and gate level design of realtime high speed (100 mhz)
digital systems utilizing Actel and Xilinx Field Programmable Gate Arrays, Verilog, Vhdl,
Synopsys, and Viewlogic schematic capture.
Currently conducting
Verilog/VHDL benchmarking on Actel & Xilinx FPGAs.
Feb. 1995 to Dec. 1996
IBM Corp., Dept. 2S9, Server Performance Analysis,
Research Triangle Park, NC.
Design Engineer, duties include:
System level design of realtime high speed digital systems capable of collecting data
at 1600 mbytes/second
utilizing Actel and Xilinx Field Programmable Gate Arrays, Verilog, Vhdl,
Synopsys, and Viewlogic schematic capture.
Aug. 1992 to Feb. 1995
IBM Corp., Dept. 96S, System Performance Evaluation,
Boca Raton, FL.
Design Engineer, duties included: Design of high speed digital
systems (66 mhz) for collecting trace data from X86, Pentium, and P6 based
systems. Implementation of "processor like" functions in Actel
FPGAs. "Beta" test site for Actel place and route
software. Multi-module simulation utilizing Viewsim. AIX/Unix
system administrator for a network of Risc based workstations.
Creation of post processing software (utilizing "C" and "C++")
for validating and analyzing trace data.
Published author
on the use of FPGAs to shorten development cycles in products for
emerging markets. Pioneer in the use of hierarchical design
techniques for printed circuit board design on Viewlogic/PCAD
based CAD systems. Extensive experience with the AFS file
system and networked systems using TCP/IP.
(Click HERE for more detail)
IBM Coordinator: M. Lydon, 919/543-5117.
Mar.1991 to Aug.1992.
IBM T.J. Watson Research Ctr, Dept 523, System Performance Analysis,
Hawth., NY.
Design Engineer, responsible for design of custom hardware to
trace and measure the performance of various Intel X86 based
systems. Viewlogic, Palasm, and ORCAD development & simulation
tools used for "chip level" designs utilizing Actel FPGA's
along with various high speed PALs. Cadence/Valid-Allegro development
tools used to implement board level designs based on "Fast" and
Advanced BiCMOS logic families.
(Click HERE for details)
IBM Coordinator: Joe Morris, 914/784-7432.
May 1990 to Nov. 1990.
IBM Corp., Dept. 26T, Mobile Solutions Development, Boca Raton, Fl.
Design Engineer. Duties included chip level design of various
PALs and FPGAs to replace existing discrete "System Board"
logic achieving a reduction in size and power consumption for
the IBM PC Radio (Invention Disclosure #BC8-91-0132). Design,
simulation, and testing carried out using the Actel ALS FPGA
development system, along with the ORCAD schematic capture
system. (Click HERE for detailed description)
IBM Coordinator: Stephen Still, 407/982-0078.
Sept. 1989 to May 1990.
IBM Corp., Dept. 96S, Custom Products, Boca Raton, Fl.
Design Engineer and Systems Integrator. Duties included debug
and redesign of PC based "Point of Sale" terminals, utilizing
programmable logic devices and P-Cad schematic capture software. (Click HERE for detailed description)
IBM Coordinator: Frank Fado, 407/443-2482.
Apr. 1987 to Nov. 1988.
IBM Corp., Dept. 96S, Custom Products, Boca Raton, Fl.
Design Engineer and Systems Integrator. (Click HERE for detailed description)
IBM Coordinator: Bill Totten, 407/443-2558.