Hints & Examples

Timing Constraint Files for Xilinx FPGAs

Design Example #1:

A cst file that specifies the max timing from REG6 to REG12 through NET9 to be 15 ns:
timegrp="fastpath=ffs(NET9)";
timespec="TS01=FROM:ffs:TO:fastpath=15";

A cst file that specifies the max timing from REG6 to REG12 through NET9 as well as REG8 to REG14 through NET11:
timegrp="fastpath=ffs(NET9:NET11)";
timespec="TS01=FROM:ffs:TO:fastpath=15";

The next example uses the same timegrp statement to spec the time from REG12 to REG18 and REG14 to REG20 by swapping positions in the timespec statement:
timegrp="fastpath=ffs(NET9:NET11)";
timespec="TS01=FROM:fastpath:TO:ffs=15";

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