Design Details
Revision B., last modified 01/16/96
Last completed design consisted of a multible 64 bit bus system, the
front end running at 66mhz, the back end running at 50mhz. FPGAs were
used to implement "processor like" functions in high speed logic; high
speed synchronous fifos were used to mate between the the two bus speeds.
FPGA designs totaled 40-50k gates (multimodule); due to high speed and
high gate counts, little HDL work would meet spec, so a top down
hierarchical design methodology was implemented in
Viewlogic
schematic capture.
Subsystem design was implemented on 14" X 14" six layer pc boards using
Viewlogic
schematic capture,
PCAD
PCB tools, and the
Cooper Chyan shape based router.