Advanced Verilog Design Techniques Hands-On WorkshopHands-On

Course Description

In the Advanced Verilog Design Techniques course, you will learn efficient coding techniques for Verilog synthesis, particularly for Altera^® devices. You will gain experience writing behavioral and structural code and learn how to effectively code common logic functions including registered, memory, and arithmetic functions. This course also introduces you to testbenches and the common ways to write them. This course is designed to be independent of synthesis and simulation tools, although your class will use the tools available at the training site for the hands-on exercises. You will also use the Quartus^® II software for placement and routing.

Skills Required:

·        Completion of the Introduction to Verilog HDL course or some prior knowledge and use of Verilog hardware description language (HDL)

·        Background in digital logic design

·        Understanding of synthesis and simulation processes

Skills Developed:

• Developing coding styles for efficient synthesis when:
• Targeting device features
• Inferring logic functions
• Using arithmetic operators
• Writing state machines
• Targeting different synthesis tools, particularly Synplicity's Synplify Pro software, Mentor Graphic’s LeonardoSpectrum^™ tool and Synopsys' FPGA Compiler II tool, and the Quartus II design software
• Implementing intellectual property (IP) and other functions in Verilog designs
• Writing testbenches for verification
• Writing parameterized designs