![]() |
![]() |
Overview:
The Xilinx® Virtex-II Pro™ Platform FPGA family offers a compelling new
alternative to ASIC-SoC for embedded systems developers. The new
capabilities of the Virtex-II Pro architecture, including an embedded
PowerPC 405 processor and RocketPHY 10GB serial transceivers, present
design challenges that require sophisticated system-level design and
verification throughout the development process. Mentor Graphics is the
only EDA company to provide a comprehensive set of Virtex-II Pro design
tools that encompass project and complexity management, functional
verification, hardware/software co-verification, synthesis and board
design.
During this technical session, learn how to:
Seminar Agenda:
Continental Breakfast | 8:30 am - 9:00 am |
Mentor FPGA Design Flow Overview | 9:00 am - 9:30 am |
Xilinx Virtex-II Pro | 9:30 am - 10:00 am |
Integrated Design Flow - FPGA Advantage | 10:00 am - 10:45 am |
Break | 10:45 am - 11:00 am |
RTL and Physical Synthesis - Precision | 11:00 am - 11:30 am |
Hardware/Software Co-Verification - Seamless | 11:30 am - 12:00 pm |
Break | 12:00 pm - 12:15 pm |
FPGA Configurability and the Nucleus RTOS | 12:15 pm - 12:45 pm |
Conclusion and Product Demos | 12:45 - 1:15 pm |