Composite Resume

For more information contact Adapticom, Inc. 919-870-0608

Revision "G" 06/22/2016

To apply wide range of software development, electrical engineering, and mechanical engineering skills creating innovative and useful solutions for your company or organization.


Decades of invention, creativity and technical innovation. Android and iPhone application development; web development via Ruby on Rails, creation of both augmented and virtual reality environments. Electronic design of FPGA & ASIC devices including Telecom, Network, Video, Rf, Optical network, Processor and Network applications.  Professional troubleshooting, specialized in computers, networks, and industrial controls, with experience at finding time critical solutions at the project, system, and device level.  Assignments accepted anywhere in North America.  Well developed skills for:

Equally at home in high level meetings or in the lab for all night work efforts.  Skilled at leading teams for on-site and off-site rework and reconfiguration issues, as well as rapid deployment and setup of temporary laboratories.  Experienced at sudden travel to impromptu meetings for securing customer satisfaction. Expert at representing the interests of the client during interaction with their customers and vendors.

Modem design, Harris (Harris/Stratex) TRuepoint TR5000: Complete integration of modem firmware in VHDL.  Validation and test of modem module hardware.   Recommendation and execution of engineering change orders as required.  Hardware testing, including verification of transmit and receive IF circuitry.

Experienced with digital, analog, and mixed signal hardware design from DC to RF.  Current experience with microwave transmission designs (modems, multiplexers, demodulators, interpolation filters, Farrow structures, etc.) implemented in VHDL and Verilog targeting FPGAs. Design of point-to-point SONET / PDH / Ethernet digital radios.

Design experience with embedded microcontroller system hardware and software design and C programming; digital video system design; image processing and computer vision algorithms and theory; implementing 1D, 2D and 3D signal processing algorithms in hardware, software, and FPGA's; Altera CPLD and FPGA design; embedded C programming of PC's for system control; motion control using stepper motors; PID algorithm development for control of DC motors; power circuits using MOSFETs and thyristors, design of user interfaces; design of high speed, complex multilayer surface mount and through-hole PCB's; interfacing with various UL and FCC compliance testing procedures. Also skilled in handling project management of small teams of technical personnel; concurrent design; reverse engineering; writing reports; working trade shows; creating product literature; doing feasibility studies; preparing proposals; writing technical papers; and giving presentations. Able to quickly grasp key points and understand how they relate to a project. Makes conceptual leaps beyond the current problem. Work well in a fast paced environment and can quickly learn new material. Projects worked on are or have been used in consumer, industrial, medical, research, and military markets.  System designs for custom test equipment and consumer products, including VoIP and Wireless (802.11b) products, using both discrete logic, chipsets, and FPGAs.  Recently completed the design, implementation, and roll-out of a low-cost IP Video Surveillance system for small businesses, based on networked cameras and other devices to provide images and live video on demand.  Successful designs using Actel, Altera, & Xilinx FPGAs and FPSoCs, along with commercial processors and chipsets, for the development of timing, FPGA security, and data separation applications, utilizing Verilog, Modelsim, Viewlogic, & Orcad from both Unix and Windows based platforms.  Expertise in issues such as certifications (Part 15, Part 68, etc.), EMI mitigation, pipelined synchronous designs, clock skew, ground bounce, termination and ringing control.  Intimate knowledge of Intel based processor architecture, including "CPU bus" characteristics, as well as Internet Appliance processors and associated DSPs.  Recent involvement with Motorola 56800E family of hybrid microcontrollers, utilizing CodeWarrior and Processor Expert .  Experienced in the use of logic analyzers and sophisticated test equipment along with development of custom tools, including data collection hardware, for instruction and address tracing of microprocessor bus activity during benchmarking.  Software / admin experience with "C"/"C++" and Perl in Linux/Unix/AIX and Windows environments.  Recent experience also includes consumer product development (VoIP, HTTP, FTP, TCP/IP, RS232) as a project and design lead with experience in embedded Linux, digital design (Motorola microprocessors, PLDs, FPGAs, simulation), analog design (A/D, D/A, DC/DC, AC/DC), & PCB design

C for embedded PIC microcontrollers (Bytecraft and Microchip), C for PC (Microsoft, Watcom, DJGPP (GNU)), QBASIC, OrCAD Capture (schematic) and Layout (PC board design) Version 9.2 for Windows, OrCAD SDT Version 4, Microchip MPLAB, Altera Quartus II (VHDL) and Maxplus II (schematics and AHDL) FPGA and CPLD design, AMD PALASM PLD design, Design Computation DC-CAD PCB design, Microsoft Windows xx, Word, Excel, and MS-DOS, Adobe Photoshop.  Software / admin experience with "C"/"C++" and Perl in Linux/Unix/AIX and Windows environments.  Recent experience also includes consumer product development (VoIP, HTTP, FTP, TCP/IP, RS232) as a project and design lead with experience in embedded Linux, digital design (Motorola microprocessors, PLDs, FPGAs, simulation), analog design (A/D, D/A, DC/DC, AC/DC), & PCB design


Adapticom Inc., P.O. Box 91461 Raleigh, NC 27675-1461 919-870-0608
ElectronicEngineer; management of Adapticom Engineering Team.  Conducted analysis of Actel, Altera & Xilinx FPGA security vulnerabilities (bitstream security & encryption, configuration corruption, data separation, TMR, microprobing, Focused ION Beam workstations, Electron Beam Testers, decapping, power analysis, Lithium Niobate, data remanence, SEU & SEL, etc.).  Currently providing clients with new product development expertise. 

Additional projects:

Northrop Grumman Corporation - FPGA/VHDL Design Engineering
Above 3 designs include: Electrical circuit design, component placement, documentation and specification, hardware/software interface, test procedure and features,  FPGA design and verification in VHDL, synthesis, and  FPGA place and route.

Design Engineer for major electronics manufacturer:     Performed timing analysis / board simulation and wrote Verilog test bench for customerís next generation router blade.  Wrote Verilog data-path FPGA (Xilinx) in RF telemetry system.  Consulted on implementation of multi-channel JPEG video system in Xilinx FPGA.  Wrote DO-178 compliant micro-controller code (PIC 18F6620) for real-time bleed air control system.  Wrote DO-254 compliant VHDL test bench (Xilinx FPGA). 

Chief electronics engineer for a major producer of O gauge model electric trains for the hobby market. Led the design of a new remote control system that uses a bidirectional 915 Mhz RF link. Did all hardware design and PCB layout for the handheld controller, the engine transceiver, and a serial port adapter that allows interoperability with other legacy systems. These 3 parts of the remote control system all use the Chipcon CC1010 transceiver / 8051 embedded microcontroller chip. Designed all peripherals that interface to this chip. The handheld includes an LCD, keypad, NiMH battery charger, several audio components, and the CC1010 RF microcontroller. The transceiver includes a small switching regulator, several MOSFET drivers, LED drivers, serial interfaces, and the CC1010. The serial port adapter includes two RS-232 serial ports and the CC1010. Designed the hardware and PCB for an audio playback board that uses the Microchip dsPIC30F210 DSP controller chip with an Atmel Dataflash for sound storage and a 2-watt audio amplifier. Performed the application level programming for this using C. It plays back 4 channels of 1/2 CD quality audio for realistic train sounds. Designed hardware, PCB and software using C for a 120 Watt hobby transformer that uses a Microchip PIC microcontroller to control triac triggering, handle over current protection and sample the control knob. Designed hardware, PCB and all software using C for several DC motor controllers using PIC microcontrollers and a PWM MOSFET H bridge motor driver. This board is closed loop and uses a PID control algorithm to regulate motor speed. The transceiver, audio and motor PCBs are all physically small with fine pitch SMT components on both sides. Designed numerous pieces of test hardware and software to program and verify functionality of these various products. A patent for the remote control system has been applied for.

Designed multi-card data acquisition system using floating point DSP, FPGA (wrote Verilog code), and 24-bit data converters.   Reverse-engineered firmware for embedded 8051 microcontroller.   Wrote firmware for embedded PIC microcontroller.   Performed Voice over IP access device design review for client.   Created client feasibility study for a custom alarm system.   Created client feasibility study for an embedded point of sale computer system.  
Circadiant Systems - FPGA/VHDL/PCB Designer.      

Designed test card to validate clock distribution and recovery scheme for next generation Digital Loop Carrier.  Wrote Verilog code to handle inter-ASIC communication and proprietary serial bus.  Provided early board and system verification for a Lucent prototype framer/mapper/multiplexer ASIC.  Analyzed and solved intermittent data loss problem with two previously fielded DS2 multiplexer cards preventing recall.  Mentored junior engineers in Analog Workbench. 

Built and debugged a 24-bit data acquisition system to detect the acoustic signature of turbulent blood flow associated with coronary artery disease.  Designed multiple printed circuit boards including a power control module based on a PIC microcontroller.  Responsible for a myriad of system integration, user acceptance, manufacturing, and compliance issues. 

Consultant to Adapticom, Inc., Raleigh, NC.
Analog and digital circuit designs and PCB layouts.  Triac based design for air-bed inflators.  Research, evaluations, and reference designs for various subscriber line interface circuits and CODEC's for Internet telephony.  Evaluation and analysis of SLIC / CODEC interface to solve an echo problem in a VoIP box.  Design of a switched mode boost power supply for a telecom fan rack.

Pivotech Systems - PCB/FPGA/CPLD/Verilog Designer

FPGA, CPLD, DSP and Analog interface (AFE) circuitry.

Embedded, digital, analog, and mixed signal circuit, system, and PCB design. Also, logic design and intellectual property creation using Altera FPGA/CPLDs, and high speed digital video and digital signal processing. Clients have included:  Elliott Technologies, Apex, NC, Adapticom, Raleigh, NC, EEDynamics, Cary, NC, and Aspex Inc, New York, NY, ITS, Raleigh, NC
Prime contractors have included:  Net2Phone, Firetrol, Lockheed Martin, AlaCart, ADS, and numerous others.
Projects included:

Actel Corporation - FPGA/VHDL/Verilog Designer IBM Microelectronics Division - FPGA/VHDL Designer
Tellium, Inc. - FPGA/VHDL Design Engineer Lucent Technologies - ASIC/FPGA/VHDL Designer IBM T.J. Watson Research Center - ASIC/FPGA/VHDL Designer Desk Net Systems - FPGA/PCB Design Engineer Kearfott Guidance and Navigation - Design Engineer
Applications of electronic imaging.  Projects  for Aspex' products and for clients of Aspex on a consulting basis:

 GNOSSP and RTIVP SBIR contracts
Applied for and received two Phase 1 and two Phase 2 Small Business Innovation Research (SBIR) contracts from the US Department of Commerce - NIST totaling $500,000.  The projects developed a prototype of the Generic Neighborhood Operator and Scale Space Processor, hardware that computes vectors of partial derivative images up to fourth order at selectable scale space filtering (similar to wavelets), and the Real Time Image Vector Processor, hardware that computes projections on vectors of these partial derivative images.  The combined system performs machine vision and image pattern recognition at video frame rates. The hardware consists of 21 ten-layer 9U x 400mm VME circuit cards. The system processes at rates in excess of 50 billion arithmetic operations per second with the image processing performed in custom logic in Altera FLEX FPGA devices.

Multifunction I/O board, an ISA card for use in the Aspex Spintrak product.

Hardware, software, and the mechanical design for a machine vision inspection system that measured extruded tapered filaments for QC purposes.  The system measured filaments' length, diameter, taper, curl, and other parameters, and reported the results. It included stepper motion control, a video camera and microscope, a frame grabber, lighting, and a computer. Wrote all control and image processing software in 32 bit Watcom C. These filaments are used in paintbrushes.
VL Frame Grabber
Design of monochrome video frame grabber board for use with VESA Local Bus (VL Bus) PC's. The board featured genlock, low noise, and programmable sample rates, offset, and gain. Images were memory mapped and data was transferred to the CPU at up to 66 Mbytes per second. It was used in Aspex' Spintrak 2000 inspection system from

Co-managment of initial product development.  Automated inspection microscope used by the synthetic fiber industry for inspecting spinnerets. It uses machine vision to inspect the dimensions and cleanliness of the spinneret's capillaries. This system continues today to be Aspex' main product and well over 100 systems have been sold to date worldwide. 

Hollow Fiber Inspection System, Althin Medical Inc. Miami Lakes, FL
Hardware, software, and the mechanical design for a machine vision inspection system that measured the inner diameter and wall thickness of hollow fibers with one micron accuracy in real-time as they were being extruded. The system included motion control, a video camera and microscope, a frame grabber, lighting, and a computer. Wrote all control and image processing software in Microsoft C. Invented the optics used to properly image the outer and inner diameters. These fibers are used as filters in kidney dialysis equipment.

Neuromedical Systems Inc. (NSI), Suffern, NY
Consulting Engineering Manager and team leader of the design of the prototype PAPNET Cytological Screening System. Integrated the Aspex PIPE image processor with a computer controlled microscope and an HNC neural network coprocessor to create a system that automatically identified areas on microscope slides of pap smears as suspicious for cancer cells. Responsible for primary image processing and machine vision design, overall system design and project management of a staff of 10 programmers and technicians. Got initial proof of concept functioning in less than six months. Partly as a result of this work, NSI ultimately raised investments of approximately $135,000,000. Received two US patents from this effort. These patents and all of NSI’s IP are now owned by Tripath Imaging of Burlington, NC.

PIPE Model 1 Image processor
Principal architect of the Aspex PIPE Model 1 system and co-managed its development into a product. It was a programmable, parallel image processor that combined the flexibility of a general-purpose processor with the speed of custom hardware. It processed images at up to 1.2 billion operations per second. The processors were made of parallel custom hardware built with up to 5000 SSI and MSI integrated circuits. Designed the programming environment for the PIPE, which consisted of a windowing graphical user interface in 1986, well before the popularity of today's GUI's like Windows. Co-wrote the business plan for this product which helped raise $500,000 in investment. The PIPE was given an IR-100 award as one of the 100 most innovative products of 1986 by R&D magazine. About 42 systems were sold to customers including the Navy, Army, NASA, NIST, Lockheed, LTV, General Dynamics, FMC, MIT Lincoln Labs, Neuromedical Systems, and the University of Wisconsin, and to research centers in China, Korea, and Taiwan.

 Scan Converters, Diagnostic Retrieval Systems Inc. (DRS), Oakland NJ
Invention, conceptual design and proposal writing for a digital radar scan converter that converted rho-theta radar data into X-Y graphical images using a reverse conversion technique. Did signal processing design and co-designed hardware for digital CFAR clutter reducing circuitry. DRS sold six systems to Elbit Ltd. of Israel. Designed a digital radar signal simulator on a Multibus platform for testing the scan converter. Was part of the team that did the conceptual design and proposal writing for DRS' bid for the US Navy's AN/SPA-25G digital radar scan converter system.

Tytem, Medical Laboratory Automation Inc. (MLA), Pleasantville, NY
Designed overall architecture and all electronic hardware for Tytem, an 8085 microprocessor controlled blood bank centrifuge. It included an embedded 8085 processor that controlled the speed, user keypad, and display LED's. Also designed the SCR motor speed controller. Took this project from proposal to production. MLA produced over 1000 of this product under contract to Ortho Pharmaceuticals.

Video and audio projects for various customers
-Designed video digitizing sections of a video frame store that was used by researchers at the National Bureau of Standards (NBS, now NIST) as the range sensing robotic vision system for the Automated Manufacturing Research Facility (AMRF). Aspex sold 6 systems.
-Designed and constructed a prototype 1 kW switching amplifier (class D) used to drive a subbass woofer loudspeaker. Twenty-five years later, class D amplifiers are now becoming popular. Implemented upgrades and modifications to several high fidelity loudspeaker systems. Part of the design team of the Ohm Walsh 2 speaker system.
-Did various video circuit design projects for a small TV commercial studio.

20040239268, Grubba, R., Luck, R., Toombs, T., “Radio-linked, Bi-directional control system for model electric trains” (applied for in 2003)
5,257,182, Luck, R., and R. Scott, "Morphological Classification System and Method" (1993)
5,287,272, Luck, R.,et. al. "Automated Cytological Specimen Classification System and Method" (1994)
Published in 14 papers in various conference proceedings including SPIE and Electronic Imaging conferences.         
Luck, R., "Some Applications for the PLDSP Reconfigurable Signal Processor", Proc. SPIE Conf. on Reconfigurable Technology: FPGAs for Computing and Applications, V.3844, 61-69 (1999).
Haines, A, and McCord, C., March 29, 1993 issue of Electronic Engineering Times, "FPGAs Bring Greater Mobility to Wireless Systems"xxxx
Luck, R., R. Tjon, L. Mango, J. Recht, E. Lin, J. Knapp, "PAPNET: An Automated Cytology Screener using Image Processing and Neural Networks", Proc. SPIE 20th AIPR Workshop, V.1623, 161-171 (1991).
Luck, R., "Integration of Real Time Systems: Image Processing and Image Feature Extraction", Proc. Elect Imaging West '91, 253-256 (1991).
Rangachar, R., T-H Hong, M. Herman, R. Luck, "Analysis of Optical Flow Estimation Using Epipolar Plane Images", US Dept. of Comm., NIST, NISTIR 4569, (1991).
Rangachar, R., T-H Hong, M. Herman, R. Luck, "Three Dimensional Reconstruction from Optical Flow using Temporal Integration", US Dept. of Comm., NIST, NISTIR 4570, (1991).
Rangachar, R., T-H Hong, M. Herman, R. Luck, J. Lupo, "Real-Time Differential Range Estimation Based on Time-Space Imagery Using PIPE", Proc. SPIE Real-Time Image Processing II, V. 1295 (1990).
Luck, R., "ASPIPE: A Graphical User Interface for the PIPE System", Proc. SPIE Conf. on Image Understanding and the Man-Machine Interface, V.1076, 180-190 (1989).
Luck, R., "Multiple Object Analysis Using a Real Time Connected Component Processor", presented at Electronic Imaging East '89.
Luck, R., "An Overview of the PIPE System", Third Int'l Supercomputer Conf, Vol III, Boston, MA, (1988).
Luck, R., "Translation, Scale, and Rotation Invariant Pattern Recognition Using PIPE", Proc. Electronic Imaging East '88", 909-918 (1988).
Luck, R., "Implementing an Image Understanding System Architecture using PIPE", Proc. SPIE Conf. on Automated Inspection and Measurement, V.849, 35-41 (1987).
Luck, R., "PIPE: A Parallel Processor for Dynamic Image Processing", Proc. SPIE Conf. on Image Understanding and the Man-Machine Interface, V758 (1987).
Luck, R., "Using PIPE for Inspection Applications", Proc. SPIE Conf. on Automated Inspection and Measurement, V.730, 12-19 (1986).

Fairleigh Dickinson University, Teaneck - Honors, BS – Electronics Engineering
Polytechnic University, Hawthorne, NY, MS – Computer Science
State University of New York at Albany, BS - Atmospheric Science with minor in Computer Science


Verilog "Hands On" Workshop :  Course teaches Verilog HDL and its use in programmable logic design.  Emphasis is on the synthesis constructs of Verilog HDL, along with simulation constructs. In hands-on labs, knowledge is utilized to create practical designs

Xilinx ChipScope Workshop Xilinx ChipScope Pro 6.1 , Jan. 2004

Cypress "PSOC Reloaded" Seminar, Nov. 2003

"Mentor Solutions for Designing & Verifying your Xilinx Virtex-II Pro FPGA" Seminar, Mentor Graphics - Xilinx, Nov. 2003

Motorola 568323 Hybrid Microcontroller Workshop, October 2003

ISDN Technology and Applications , July, 1996. Instruction and materials from N.T.U.  

High-Speed Computer Networks , June, 1996. Instruction and materials from N.T.U.

Intro to Java , May., 1996. Instruction and materials from N.T.U.

Learn Perl Now! , May., 1996. Instruction and materials from N.T.U.

Tutorial On Use of VHDL For Description of Digital Systems , Mar., 1996. Six hour course, instruction and materials from N.T.U. (Certificate of Attendance)

Advanced VHDL Topics; Top Down Design Methodologies , Jan., 1996. Six hour course, instruction and materials from N.T.U. (Certificate of Attendance)

Characteristics of Intel's Pentium Pro (P6) , Nov., 1995
Eight hour course, instruction and materials IBM.

Pentium Processor System Architecture II , Nov., 1995
Twenty hour course, instruction and materials from Don Anderson & Tom Shanley.

The Shapetek (Cooper & Chyan) Adaptive Autorouter , Model 50, Feb. 1994.
Eight hour course, instructor and materials from Offsite Solutions, Orlando, Fl.

AIX System Administration , Jan., 1994
Twentyfour hour course, instruction and materials from Skill Dynamics.

Pentium Processor System Architecture , Dec., 1993
Instruction and materials from Don Anderson & Tom Shanley.

Introduction to AIX and the Andrew File System , November 1993.
Sixteen hour course, instructor and materials from Boca Raton Technical Services.

Designing with Powerview , September 1993.
Sixteen hour course, instruction and materials from Viewlogic Corp., Marlboro MA.

Synopsys VHDL Synthesis & Simulation Workshop , March 1993.
Forty hour course, instruction and materials from Synopsys Inc., Mountain View, Ca.

PCAD Master Designer 6.0 Printed Circuit Board Design Course , Feb.., 1993.
Forty hour course, instructor and materials from Technical Systems Integrators and PCAD.