ERIK PILMANIS

919-870-0608

(word version)

SUMMARY   Over 21 years experience in digital hardware engineering including:

·        Experience in High Speed hardware design.
·        FPGA, ASIC, and PCB design including: Telecom, Network,Video, RF, Optical network, Processor, and Network applications.

·        Expertise in VHDL and Verilog HDL: Synthesis, Modeling, andfunctional/gate/system/post layout level verification.

EXPERIENCE

Adapticom Incorporated                                                    Raleigh, NC

11/2005 – Present :  Consultant, FPGA/VHDL

·        Consultant on FPGA & VHDL tools & projects.

Northrop Grumman Corporation                                                     Norwalk, CT

9/2003 – 11/2005 : FPGA/VHDL Designer.

·        HDL verification for NGC’s  Direct Digital Synthesis ASIC. Test bench designed in VHDL to verify DDS ASIC models.

·        Hardware verification for NGC developed DDS ASIC. Designed a high speed test system used to operate the DDS ASIC under varying in-circuit conditions. Design included: PCB design, FPGA design and verification in VHDL, host interface, hardware and software specification, and software co-design.

·        Designed/Simulated Direct Digital Synthesis interface FPGA for Multi Mode radar platform implemented in a Xilinx Spartan III FPGA. Design connected a proprietary bus standard to a custom DDS ASIC, and generated timing/synchronization signals.  

·        Designed/Simulated L and X Band Synthesis interface FPGA for Multi Mode Radar system implemented in a Xilinx Spartan III FPGA.  Circuit operation was achieved with no external synchronous clock and utilized available asynchronous signals for timing.

·        Designed/Simulated Channel Correction FPGA design implemented in a Xilinx Virtex II Pro P70 FPGA including a 128-tap/32 bit precision FIR filter running at 270 MHz (540MHz input data rate). FIR filter speed was achieved by generating RLOC routing directives within the VHDL code. Automatic 4 channel clock to data phase correction circuit designed to align multiple frequency data streams to selectable input clocks.  

·        Digital IQ Demodulator Bus Interface FPGA implemented in a XILINX Virtex II Pro P70 used to connect host Tundra PCI/VME bridge to FIR filter and Serial FPDP FPGA’s including 2 DIQ ASIC’s. Design supports VME 32 and 64 bit bus standards.      

·        Designed/Simulated Serial FPDP SERDES/MGT design implemented in a XILINX Virtex II P70 FPGA. 4 Systran Serial FPDP cores were used in conjunction with data steam framing, header insertion, and multiple AGC mode designs(system speed 250Mhz).

Northrop Grumman Corporation  Continued

·        All above designs written and simulated in VHDL utilizing the following tools: Modelsim SE 5.6, Synplify Pro 7.3.4, Xilinx ISE 6.2.2, and HDL

           Designer Pro.    

·        Architected and designed high speed Digital IQ card test system utilizing a 2 component PCB module. Features include: High speed LVDS vector generation and interface, RS232 and Ethernet host interface, VME bus

exerciser and analyzer. Test vector generation and capture accomplished through the use of a Xilinx  Virtex II Pro P2 FPGA with MicroBlaze soft processor, host interface, and host test application.  

·        Architected and designed Digital Interface card test system utilizing a 3 component PCB module. Features include: RS422/RS485/LVDS interfaces to the UUT, RS232/Ethernet/USB host interface, Xilinx Spartan III FPGA for vector generation and capture.

• Architected and designed high speed ASIC test PCB system capable of testing 2 ASICs simultaneously at over 500MHz.  Xilinx  Virtex II Pro P70

FPGA used to generate and capture test vectors from MATLAB generated files. Test vector execution and control achieved through a RS232 host interface.

• Above 3 designs include: Electrical circuit design, component placement,

Documentation and specification, hardware/software interface, test procedure and features,  FPGA design and verification in VHDL, synthesis, and  FPGA place and route.

Circadiant Systems                                                                       Allentown, PA

4/2002 – 9/2003 : FPGA/VHDL/PCB Designer.      

• Xilinx Virtex II 6M gate SOC design utilizing: 10Gb/S LAN/WAN/HDLC packet generators and receiver for 10Gbe LAN/WAN and OTN port interface. Design produced 10Gbe LAN/WAN and PPP protocols with embedded IP packets. Design features included: multiple traffic profiles, static/ramping address fields, configurable LLC/SNAP fields, MPLS tags and HDLC link negotiation. Other design blocks included: Processor interface, PCI core, interface to: framer, digital wrapper, cross point, and transponder devices. System design speed 180MHz.
• Xilinx Virtex II 6M gate 10Gbe LAN/WAN and OTN cross point switch. Designed a 622 – 670MHz FPGA cross point data path utilizing: Variable DCM phase shift adjustment, automatic data/clock phase adjustment, 670 MHz clock forwarding, and OC192/OTN add/drop processing. Design was successfully implemented using auto/manual routing/placement and floor planning.
• PCB electronic design for 670MHz OC192 and OTN port interface utilizing: above FPGA designs, high speed LVDS and HSTL data path to the switch FPGA, SONET framer, digital wrapper/FEC device, full duplex PLL designs with scaleable frequency dividers for OTN device, Optical transponder, and power supplies.

Pivotech Systems                                                                        Piscataway, NJ

11/2001 – 4/2002 : PCB/FPGA/CPLD/Verilog Designer

• Designed C- PCI 6U 16 Port G.SHDSL and T1 framer PCB utilizing:

FPGA, CPLD, DSP and Analog interface (AFE) circuitry.

• Designed C- PCI 3U 16 Port G.SHDSL and T1 RTM PCB analog card.
• Both cards were designed in compliance with: FCC86, Bellcore 1089, UL 1950, ITU- TK.20 and FCC20.
• Xilinx Spartan II and 95144XL used as programmable logic with: Synopsys FPGA compiler, ModelSim and Xilinx alliance.
• Orcad Capture used with PADS to design and route both PCB designs.

Actel Corporation                                                                      Mt. Arlington, NJ

10/2000 – 11/2001 : FPGA/VHDL/Verilog Designer

• CPCI PCB interface design for Ethernet/ATM switch card.
• CPCI PCB bus arbitration design for Ethernet/ATM switch card.
• Above designs implemented with Xilinx Virtex II and 9500 PLD’s with Synopsys, Cadence-Verilog XL, and Xilinx Alliance and Xilinx Web Pack development systems.

• Designed 400 MHz Quad Data Rate SDRAM controller evaluation PCB including:
• 200 MHz SSTL2 DDR SDRAM controller (Xilinx Virtex).
• 400 Mhz SSTL2 QDR SDRAM controller (Xilinx Virtex II).
• Above designs implemented in Xilinx Virtex II FPGA’s with Synopsys Design Compiler, MTI’s ModelSim, Xilinx Alliance and Exemplar tools. Extensive hand placement and design of Virtex FPGA’s utilized to achieve desired system speed and reliability.
• Test controller/host interface design for QDR SDRAM controller. Design used Actel SX series FPGA’s and development system.

IBM Microelectronics Division                                                       Hopewell, NY

5/2000 – 10/2000 : FPGA/VHDL Designer

• Designed PCB and FPGA’s used to control IBM’s next generation 70 micron Electron Beam lithography system (Beam positioning and Timing system).
• FPGA and CPLD designs utilized Altera Flex20K and MAX 7000 programmable logic families.
• PCB electrical design accomplished with Viewlogic Designer tool suite.
• FPGA, CPLD and system level simulation in VHDL utilizing: ModelSim, and Viewlogic speedwave simulators.
• FPGA and CPLD synthesis performed with Exemplar and Synopsys.

Tellium Inc.                                                                                     Oceanport, NJ

11/1999 – 5/2000 : FPGA/VHDL Designer

• Designed FPGA’s used to control SONET switch cross connect system:
• Motorola PPC 860 CPU interface.
• Designed TDM highway communications link including error correction and detection.
• SONET OC48/192 overhead frame monitoring and Add/Drop processing.
• Designs utilized Xilinx Virtex and Spartan FPGA families.
• 250K and 150K designs achieved using the following tools: ModelSim, Leonardo Spectrum/Renoir/HDL designer, and Xilinx Alliance.

Lucent Technologies                                                                     Whippany, NJ

2/1999 – 11/1999 : ASIC/FPGA/VHDL Designer

• Designed top level SOC architecture of HDTV Video Compression processor ASIC.
• Designed Video Compression Processor sub modules.
• Design utilized LSI’s G11p 250 micron Cell based technology.
• 600K gate ASIC designed with the following tools:
• Synthesis: Synopsys Design Compiler.
• Scan insertion: Synopsys DC (50% coverage).
• Static timing analysis: Synopsys primetime.
• LSI Foundry Design Kit including: Synopsys libraries, fault simulation, clock tree generation, and memory generation tools.

IBM Research Division                                                                   Yorktown, NY

8/1996 – 2/1999 : ASIC/FPGA/VHDL Designer

• Designed two versions of a base band processor utilized as a physical layer in a 10Mb/s wireless point to point LAN.
• The first design utilized the 2.4 GHz ISM band and the second was built to operate in the 5.2 GHz NII band.
• Projects were designed and modeled in VHDL and were realized first in Altera Flex10K and Actel MX series FPGA’s.
• Final designs implemented in IBM’s 5S CMOS .35 micron standard cell ASIC technology.
• Demonstrated operation of BB Processor by PCMCIA/Ethernet cards to transfer data from access point to user.
• Designs achieved with the following tools: ModelSim PE/EE, Synplify, MaxPlus2, Actel Designer, IBM’s:  High Level Synthesis, Booledozer,

           and ASIC tool suite.

Desk Net Systems                                                                             Armonk, NY

1/1996 – 8/1999 : FPGA/PCB Designer

• Designed circuitry used to debug and analyze ATM protocol networks.
• Designed a PCMCIA\ISA bus to local INTEL i960 bus interface, TX/RX ATM cell processor, and a 622Mbps (OC12) SONET physical layer card.
• Bus interface and ATM cell processor designed using Xilinx 4025 fpga’s,

and Lattice CPLD’s.

IBM Research Division                                                                   Yorktown, NY

3/1995 – 8/1996 : FPGA/PCB Designer

• Responsible for the design of MPEG2 video/audio to PCI bus encoder hardware.
• Designed Actel FPGA’s to implement chipset compatibility, data flow control, PCI bridging and PCI bus arbitration.
• Actel, Altera, Viewlogic, and Cadence tools used for design.

IBM Research Division                                                                   Yorktown, NY

3/1992 – 3/1995 : FPGA/PCB Designer

• Responsible for the design and prototyping of custom hardware used to trace and measure performance of various Power PC, i386, i486 and Pentium based systems.
• Used Viewlogic, Cadence, Actel, Altera development and simulation tools for chip level designs utilizing Actel and Altera FPGA’s along with: High speed PLD’s, FIFO memories, System bus interface, and Discrete logic devices.
• Developed custom FPGA design methodology yielding results consistently surpassing those of stock designs.

Video Technologies Corporation                                              WestMilford, NJ

5/1989 – 3/1992 : Design Engineer

• Debugged and redesigned various NTSC video sub systems including: Microprocessor controllers, controller firmware. Modulated power supplies, servo systems, stepper motor drive circuitry.

Kearfott Guidance and Navigation                                                     Wayne, NJ

2/1984 – 5/1989 : Design Engineer

• Designed/prototyped high speed fiber optic token ring network and test fixture for A7 and Space Shuttle inertial navigation system.
• Assisted in the design and testing of B1 Bomber flight computer and AC 131 gunship.
• Tested and debugged flight computer circuit cards including: CPU, memory, I/O, A/D, D/A and interfaces.

EDUCATION

BS – Electronics Engineering : Fairleigh Dickinson University, Teaneck, Honors

MS – Computer Science :  Polytechnic University                        Hawthorne, NY