High Speed Digital Design Details
Revision D., last modified 11/18/05
Recent designs consist of a multiple 64 bit bus system, the
front end running at 200MHz. Multiple FPGAs were
used to implement "processor like" functions.
A combination of GTL+, ECL, PECL, LVTTL, and TTL logic families, along with
a variety of termination techniques, were used to achieve speed and signal quality requirements.
In some instances, high speed synchronous fifos were used to mate between varying bus speeds.
Individual modules for the FPGAs were completed in Verilog
and integrated into a
hierarchical design methodology, which was implemented in
Subsystem design was implemented on 14" X 14" pc boards using
schematic capture and Allegro
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