RTS (Realtime Trace Tool) Activities

RTS (Realtime Trace Tool) Activities

Revision A., last modified 11/05/02

Jan. 1997 to Jan. 2000
Responsible for development and support for "Realtime Trace Tools" for IBM RTP. Duties included: Sub-system, module, and gate level design of realtime high speed (166 MHz) digital systems utilizing Actel and Xilinx Field Programmable Gate Arrays (FPGA's) , Verilog, Vhdl, Synopsys, and Viewlogic schematic capture. Conducted Verilog/VHDL benchmarking on Actel & Xilinx FPGAs. After an initial eighteen month design period for the Realtime Trace System, at IBM Research in Hawthorne NY, accompanied the tool to the Personal Systems Performance Lab in Boca Raton, Florida and for the next seven years acted not only as the primary source of technical expertise for the project, but also as the primary proponent and project manager for further development of the tool. Managing the project consisted of four primary elements:

Planning and executing the technical tasks associated with developing "first of" hardware.
Navigating the "political waters" within IBM and surmounting the problems associated with a complex and expensive project such as RTS.
Scheduling the hardware deliverables for the project to coincide with the latest processor technology.
Scheduling and managing the actual collection of data to match the availability of various sever "test beds" as the evolved through the Server Performance Lab.

Management featured the judicial use of outside vendors and contractors to balance the work load, along with maintaining a consistently positive relationship with IBM management, and the use of various project mangement tools such as Microsoft Project to track the progress of the individual tasks and their gating factors.

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